1. Field of the Invention
The present invention relates generally to a system and method for controlling the operation and advancement of computer pipeline stages. More particularly, it relates to such a system and method which does so in a complete, practical and simple manner.
2. Description of the Prior Art
Modern high-performance data processing systems are pipelined machines. In pipelining, the operations required to process each computer instruction are partitioned into a number of stages. Each of these "pipeline stages" performs a specific function for the execution of a machine.
Pipelining techniques were originally developed in the early 1960's. Some machines have very complicated pipelines with many stages, and the ability to have instructions skip stages, buffer instructions between stages, or even reorder instruction execution as processing progresses. In a conventional pipeline control mechanism, a control input is provided for each possible exceptional event. On the occurrence of one or more exceptional events that require a stall or interrupt during a machine cycle, it is necessary to translate and rank order these control inputs according to priority. Such translating and prioritizing can result in significant delays that increase cycle time and therefore reduce data processing throughput.
More specifically, a major complexity of conventional pipeline control methods arises from the handling of stalls and interrupts. Stalls can cause either some or all of the pipeline stages to stop, depending on the cause of the stall. Stalls are typically communicated within the CPU by a number of signals denoting exceptional conditions, such as cache miss, instruction buffer miss, page fault, interlock type x, and the like. These exceptional conditions then must be prioritized and translated into control signals for each pipeline stage.
Interrupts abort the execution of some pipestages and allow the remainder to continue execution, start executing new instructions at a system location, and change privilege operation modes. One difficulty with interrupts is choosing the instruction address ("PC") of the instruction at which to resume execution while taking the interrupt. This becomes even more complicated in the presence of multiple interrupts in the same cycle. If different interrupts have different "trap vectors", i.e., branch addresses, the interrupts must be prioritized before the proper PC can be saved for resuming execution and the execution begun at the new address.
Thus, a number of features present in the prior art require complex and slow pipeline control logic:
1. The need to prioritize exceptional stall conditions and translate these signals to control signals for each pipestage.
2. The need to prioritize interrupt conditions in order to save the PC corresponding to the highest priority interrupt, abort instructions following the cause of the interrupt, and choose a trap vector address. Since the hardware to implement this capability might be used on any cycle, it is evaluated on every cycle, and can easily set a lower bound on machine cycle time. This is further exacerbated by the fact that many of the exceptional conditions or interrupts come from distant portions of the machine and may spend a considerable amount of the cycle just traveling to a central prioritized.